In development of electronic systems, it is necessary to test such systems under varying conditions to attempt to uncover system bugs. One method of doing this is to trigger certain repetitive transactions at slightly different timing to hopefully uncover problems that would not be uncovered if these transactions are triggered only with the same timing. Ideally, random trigger signals are used in diagnostics including design verification and testing, manufacturing, in-field testing, and repair testing. The use of random time intervals improves confidence in testing. However, it is difficult to generate truly random triggering.
FIG. 1 is a block diagram of a conventional system that is configured to trigger, for example, data transfer from one device to another. In FIG. 1, the system generally shown at 1 includes device I at 2, device II at 3, and pulse generator 5. Device I and Device II are connected by cable 4. Under normal circumstances, pulse generator 5 may be part of a microprocessor or central processing unit ("CPU") which will send a trigger signal to device I to transfer data to device II. The time that the data is sent will be a certain period of time after the trigger. If this period of time is fixed some system problems may be masked, so during system development, pulse generator 5 may be replaced with a pseudo-random pulse generator which will output a trigger signal to device I at slightly different times.
D. E. Knuth, "The Art of Computer Programming," Vol. 2, pp. 9, 10, 155, 156 [1969] discusses the implementation of programs by computers or microprocessors for generating pseudo-random numbers in accordance with a linear congruential sequence. According to that text, a pseudo-random number sequence will be obtained by using the following expression: EQU X.sub.n+1 =(aX.sub.n +c) mod m (1) EQU for n.gtoreq.0
where,
X.sub.o =the starting value, PA1 a=the multiplier, PA1 c=the increment, and PA1 m=the modulus. PA1 f(i)=1 if stage B.sub.i is connected to the serial adder and f(i)=0 otherwise, where B.sub.i is a stage of the second shift register means.
A flow diagram for determining such a pseudo-random number sequence according to expression (1) is shown at FIG. 2. At 7, the microprocessor initializes the variable X.sub.n to be equal to X.sub.0. Next at 8, the microprocessor reads the modulus value m. Following this, at step 9, the microprocessor reads the multiplier value "a." The computer or microprocessor reads the increment value "c" at step 10, while at step 11, the microprocessor performs the calculation according to expression (1). The result of this calculation is a pseudo-random number in accordance with a linear congruential sequence.
The microprocessor at step 12 loads a hardware binary counter with the value computed at 11 and that value is allowed to count out. At 13, the microprocessor periodically checks the status of the counter to determine if the counter has finished counting the value loaded at 12. If the counter is not finished, the microprocessor executes a wait at step 14. When the counter is finished counting, the microprocessor sets the value of X.sub.n equal to the X.sub.n+1 value at step 15. This value was previously calculated at step 11. Thereafter, the microprocessor repeats steps 11, 12, 13, 14, and 15.
The use of a microprocessor to calculate pseudo-random number sequences for testing purposes limits randomized testing to tests requiring a relatively low number of trigger events because random number generation is slow when a microprocessor is used so the time it takes to test devices is considerably long.